This invention relates to latch circuits and, more particularly, to fast-acting low power semiconductor latches which respond to asynchronous inputs.
The prior art contains many latch circuits. The most common configuration consists of two cross-coupled gates such as a NOR-gate. The speed of this type of circuit is, however, limited by the characteristics of the pull-up device for each gate. In circuits embodied using metal-oxide-semiconductor-field-effect transistors, hereinafter referred to as MOSFETs, decreasing the length of the pull-up MOSFET reduces the switching time but it also increases the power consumption of the circuit and increases the amount of chip area used since the pull-down device must be accordingly enlarged to maintain an adequate impedance ratio.
A circuit designed to reduce the delay in such latch circuits is disclosed in U.S. Pat. No. 3,846,643, issued Nov. 5, 1974, to William M. Chu et al. This circuit, embodied using MOSFETs, operates with two independent input transistors establishing the alternative output voltage states, the first causing the high state and the second causing the low state. The output changes occur as an essentially immediate response to an input to either of the input transistors, but there is no cross-coupling of these devices and hence the output state will not remain latched when the appropriate input ceases to be received unless another mechanism causes latching. The Chu patent discloses for this purpose, a cross-coupled latch mechanism consisting of five transistors. This mechanism monitors the output state and when that state changes, it latches to the changed state causing the output to be maintained after the input is removed. However, the Chu circuit operates in a ratioed manner and causes a significant dc power drain when latched, since the cross-coupled latch mechanism provides a continuous dc path to ground in order to remain latched. The input transistors must be of relatively low impedance compared with the impedance offered by the path to ground through the latch mechanism in the preexisting state. This power consuming characteristic, as well as the limitations provided by the ratioed operation, make it desirable to find an alternative latch circuit which operates without significant delay and without the disadvantages of the Chu design.
Accordingly, it is an object of the present invention to provide a fast-acting, low power, latch.
It is a further object to provide a fast-acting, low power, semiconductor latch using a minimum number of devices.
It is a still further object to provide a fast-acting, low power latch using MOSFET devices; and
It is a still further object to provide a fast-acting, low power MOSFET latch which is ratioless in design.